1. Field of the Invention
The present invention relates to a process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, relates to the processing of chips while arranged on a wafer prior to orienting the chips into stacks. Furthermore, the invention also pertains to the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.
In essence, the basic concept of forming three-dimensional or stacked integrated circuits is well known in the semiconductor and related technology, in which the use and fabrication of multi-chip stacks are widely employed in enabling multiple and diverse technologies, and materials can be readily combined into a single system in order to provide functions which are incapable of being obtained by means of single technology and material combinations. Moreover, advantageous and versatile combinations of diverse integrated circuit structures or arrays and modules provided on chips which are assembled in multi-chip stacks can be readily obtained with the shortest leads or wires connecting the various chips, thereby resulting in a shortening of the wiring lengths while concurrently reducing the overall package area in forming the multi-chip stack. It is also possible to produce very large sized chips in the assembling of a plurality of smaller sized chips which are combined and bonded with each other, thereby increasing output of the electronic device employing the chip stacks. In some instances, the three-dimensional integrated chip structures, which are obtained through the formation of multi-chip stacks and the bonding of pluralities of smaller chips to each other in a three-dimensional stack-forming arrangement, can combine diverse technologies. This combination of technologies can enable the obtaining of advantages, such as particle-travel mapping or three-dimensional sensor. Consequently, chip stacks are often utilized in the form of so-called cubes, such as those manufactured by Irvine Sensors™ in which leads are extended outwardly from between bonded chips to a stack edge in order to afford accessibility thereto upon mounting of the chips, for example in a vertical chip array, on an underlying substrate. This, typically, requires special single chip processing on cube edges after effectuating cube stacking with fewer contact leads being accessible, and a necessity for implementing unusual packaging.
Smaller chips can be wire-bonded, while in a face-up orientation onto a larger chip. This hybrid combination, in turn, is then wirebonded to an outside carrier or C4 (controlled collapse chip connection) bonded onto special substrates, which are equipped with recesses in order to accept the so-called bump that normally is present in an attachment. Consequently, this basically-evident combination is limited to either one small or to a few very small-sized chips, which is or are bonded to a considerably larger chip, such that a significant proportion or percentage of the base wafer surface area remains available for connections of the latter to the electronic or semiconductor device package. This, in effect, forms a limitation which restricts the relative sizes and quantities of chips being formed or assembled into multi-chip stacks.
2. Discussion of the Prior Art
Although, various three-dimensional chip and wafer systems and assembling processes have been developed in the current-state-of-the-art, pertaining to this technology, these are still subject to various limitations and restrictions in comparison with the broader aspects attained by means of the present invention.
Suga, U.S. Pat. No. 6,465,892 B1 and Suga, U.S. Pat. No. 6,472,293 B2, which is a divisional of U.S. Pat. No. 6,465,892 B1, each relate to interconnect structure for stacked semiconductor devices and disclose a method of manufacture of the interconnect structures, wherein the basic concept in each of the patents resides in efforts of shortening the wiring length by superimposing semiconductor substrates and bonding these together by means of solid state bonding techniques. Although this provides for the stacking of chips, there is no formation of a multi-chip stack in a manufacturing process utilizing a flat wafer structure, whereby prior to forming and bonding the chips into stacks, all of the chips processing is precedingly performed.
Concerning Fung, et al., U.S. Pat. No. 6,355,501 B1, which relates to a three-dimensional chip stacking assembly, and which is commonly assigned to the assignee of the present application, this pertains to the forming of three-dimensional stacked SOI (silicon-on-insulator) structures. However, although this patent is directed to a method of stacking ultra thin chips with interconnections for maximizing the operational speed of an integrated circuit package, there is no disclosure of a process of fabrication and processing of all of the chips while mounted on a standard wafer prior to separation or slicing of the wafer into individual components prior to chip stacking.